Many of today's large capacity semiconductor random access memories use multiplexed input address lines in order to limit the number of external pins on the package and to make same compatible with available memories which have smaller capacity. These large capacity memories typically use several sub-arrays which have row and column decoders that must be coupled to the output address lines of an input address buffer. The silicon area needed to connect up the row and column decoders to the input address buffer increases the overall size of the memory chip and accordingly decreases yield and increases cost.
It is desirable to be able to reduce row and column address lines such that the size of the memory chip and the cost are reduced.